1. Field of the Invention
The present invention relates to a method and apparatus for address mapping. More particularly, the present invention relates to a method and apparatus for mapping an address that is accessed by a processor in a system based on a Million Instructions Per Second (MIPS) processor.
2. Description of the Related Art
In the design of a controller to be applied to a high-performance color laser printer, the use of Million Instructions Per Second (MIPS) processors has been increased to satisfy performance requirements. However, in the case of a MIPS processor, an address region of about 0.5 GB that may be accessed without setting a Translation Look-aside Buffer (TLB) is used at booting, and other address regions are extended by means of TLB settings while programs are being executed.
FIG. 1 shows an example of an address map used in a conventional system based on a MIPS processor. Referring to FIG. 1, when decoding addresses corresponding to each region allocated to a DDR controller, GDMA controller, IO controller, PCI controller, Special Function Register, ROM controller and so on, information stored in a base address register and a size register is referenced to conduct the decoding. That is, if an address to be decoded is input to a decoder logic unit, it is determined whether the address is corresponding to a [base address˜base address+size] stored in the register. A chip select (CS) signal is then generated to enable access to the corresponding region. In addition, during the program execution, a user can change values of the corresponding base address register and the size register to reallocate the corresponding regions.
For example, assume for purposes of explanation that a Double Data Rate (DDR) controller using a MIPS controller supports a DDR RAM region of 2 GB, and that 2 GB already exceeds the range of 0.5 GB that may be accessed by the MIPS processor at booting. Thus, a part of the region is mapped at booting, and this region is reallocated by means of a program after booting, so as to use the region of the 2 GB range.
In the case of FIG. 1, for a DDR region at booting, a region [0×0000—0000˜0×17FF_FFFF] having a 384 MB size is mapped. With an execution of a program, the DDR region is mapped to an address region [0×4000—0000˜0×BFFF_FFFF] having a 2 GB size by means of reallocation. Since the decoder logic unit including the base address register and size register for each region may reallocate the corresponding region, a user may generate a desired physical address.
However, such an address mapping method has a number of problems, including the following specific problems.
First, since the physical address is variable, additional measures are required to deal with the physical address. That is, if a physical address is varied, all entries mapped in the corresponding address should be changed in a TLB that is used for converting a virtual address into a physical address. In addition, if there is a pointer referred to in the corresponding address, any reference values should be changed. Thus, there are many additional considerations needed in programming.
Second, since a programmer may perform an address mapping as he desires, there are more possibilities for errors. For example, if several programmers take a project at the same time and each programmer individually sets a base address for each region, a border to any region set by any programmer may violate another region. In this case, an overlapped region results in the mapped region, which may cause unintended malfunctions.
Third, a decoder logic unit for decoding an address corresponding to each region becomes complicated and can deteriorate performance. That is, since a base address of each region is varied, combination logic for comparing a base address register and a size register is required for every region. This may be a factor resulting in deteriorating the decoding performance. Furthermore, since combination logics should preferably be added in the decoder logic unit in proportion to the number of supported regions, the complexity of the entire decoder logic is increased.
Accordingly, a need exists for a system and method for efficiently and effectively mapping an address that is accessed by a processor in a system based on a MIPS processor.